1. Field of the Invention
The present invention pertains to bus architecture in computer systems, and more specifically pertaining to terminations in a Assisted Gunning Transceiver Logic Plus (AGTL+) bus architecture using dual processors and dual memory controllers that are designed for a quad processor system.
2. Description of the Related Art
A computer system generally includes various system components coupled to one or more internal buses. Such an internal computer bus is made up of the electrical signal lines that connect the computer components. Typically, a computer bus is based on an industry standard so computer components of various types can be designed to operate on the bus. New bus designs are often introduced which provide increased bandwidth over prior bus designs.
As processors, memories, and other components increase in speed, printed circuit board (PCB) connections that allow these components to communicate with one another begin to behave like transmission lines. These transmission line characteristics were always present, but as edge rates increase and the transmission rates increase, the effective line lengths become longer and the transmission line effects become especially important -- important to the degree that if they are not addressed, the system may not work. Reflections in the transmission line cause distortions of the signal at the receiving end of the line. These distortions can cause false triggering in clock lines, can cause erroneous information on data, address and control lines, and can contribute significantly to clock and signal jitter.
Concerns previously relegated to the analog world, such as transmission line effects, are now affecting whether a digital design works at high speed. System designers have used Gunning Transceiver Logic (GTL) bus technology to address these concerns. Various versions of GTL are being implemented to ensure signal quality for the newest generation of processors.
The higher speed processors are typically used on higher speed computer buses using GTL (and its variants) bus technology. For example, a recent processor from Intel Corporation of Santa Clara, Calif., is the PENTIUM II XEON processor (herein referred to as the XEON processor). Some features of the XEON processor include a dynamic execution micro architecture, single edge contact (S.E.C.) cartridge package technology, 100 MHz system bus speeds data transfer between the processor and the system, dual independent bus architecture, and level 2 (L2) cache. These features are described in detail in the publication Intel Pentium.RTM. II XEON.TM. Processor at 400 MHz, June 1998, which is herein incorporated by reference in its entirety. The XEON processor is designed to operate in a quad (4) processor architecture, that is four multiprocessors operating on a common bus. Thus, the XEON processor or a processor of this type referred to according to the present invention as a quad processor. Operating at the higher computer bus speeds required impedance matching of all loads on the computer bus to ensure signal quality and integrity. XEON processors have their own termination circuitry for this purpose. Due to the existence of this termination, using XEON processors is not recommended in a daisy chain topology, a technique that was previously acceptable in previous Intel P6 Family processors. In a daisy chain topology, the loads, e.g., processors and memory controllers, are serially connected, one next to the other.
The XEON processor is the first slot 2 processor. Slot 2 refers to the connector of the Single Edge Contact (SEC) cartridge plugs into, just as the PENTIUM PRO processor uses Socket 8. The SEC cartridge typically includes the core processor and L2 cache memory on a single substrate. The SEC cartridge allows the L2 memory cache to remain tightly coupled to the core processor. L2 cache communication occurs at full speed of the processor core (compared to half the processor speed in the PENTIUM II processor). Furthermore, each XEON processor includes termination circuitry for the processor's AGTL+ bus to insure signal quality and integrity for communications at 100 MHz.
In addition, to maintain impedance matching with the XEON processor internal termination circuitry and timing due to data transfer rates, Intel recommends a quad (4) processor architecture with a single chipset for 100 MHz bus operation. System designers are hampered with Intel's requirements. Thus, the designers are prevented from designing efficient systems at optimal prices to meet customers needs. Other architectures, for example, a dual processor and dual chipset architecture are not recommended for 100 MHz operation. Flexibility in architecture allows designers to customize the system, emphasizing features, such as memory access, that might be desired by consumers.
To maintain signal timing and integrity of a dual XEON processor/dual memory controller/bridge configuration, the loads need to be placed close to one another. An additional constraint faced by the designer is board real estate. Board real estate is limited in a highly populated board. Additional layers can be added but cost of the board will escalate and these additional layers only add to trace lengths which have strict limits.
Although the tight design constraints for the quad processor host bus are thought to be necessary to achieve maximum performance, Intel's proposed implementation substantially limits system design flexibility and does not allow for all product requirements.
The proposed implementation is very large and expensive to build. The XEON processor alone requires several square inches of board space. The system logic to support the XEON host bus, such as the memory controller and I/O bridge also requires a large area of board space. To maintain signal integrity, the width and height of traces or the processor board must be maintained within tight tolerances, which becomes increasingly difficult as the size of the board increases.